1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a radiation-hardened semiconductor device and a method for manufacturing the same.
2. Description of the Related Art
When using semiconductor devices containing MOS transistors as components for space appliances, static consumption current increases due to effects of space rays (such as gamma-rays). When a semiconductor device is exposed to gamma-rays, hole-electron pairs are generated in the field oxide film which separates between elements, and holes having the smaller mobility of them are captured in the interface between the silicon substrate and silicon oxide film, and a fixed positive charge is formed, and the threshold voltage of parasitic N channel MOS transistor is lowered, and the conductive type of the silicon substrate surface contacting with the field oxide film may be inverted to increase the leakage current.
Conventionally, to prevent such increase of leakage current, a P type high concentration impurity region called a guard band is formed around the N channel MOS transistor to prevent inversion of conductive type of the surface of P type substrate (or P type well).
For example, in the case of gate array, as shown in the publication "A Radiation-Hardened CMOS 177 k Gate Array Having Libraries Compatible With Commercial Ones," K. Ohsono et al., 1994 IEEE Radiation Effects Data Workshop, pp. 37-40, Jul. 20, 1994 (particularly FIG. 1), against leakage within element N (leakage between the source and drain), a high concentration guard boron P layer is formed in the boundary of the source and field oxide film, and in the boundary of the drain and field oxide film, and against leakage between elements, a high energy boron P layer or high concentration boron P layer is formed around the N channel MOS transistor, and the inversion of conductive type is prevented.
Incidentally, the high concentration guard boron P layer for preventing leakage within element N is disclosed in Japanese Laid-open Publication No. 61-164265, the high energy boron P layer for preventing leakage between elements is disclosed in Japanese Laid-open Publication No. 2-304949 or Japanese Laid-open Publication No. 6-140502, and the high concentration boron P layer for preventing leakage between elements is disclosed in Japanese Laid-open Publication No. 62-5654. Moreover, Japanese Laid-open Publication No. 9-82793 discloses a forming method of a channel stopper layer contacting with the lower surface of the field oxide film
Conventional semiconductors are described below, and first a semiconductor device for general use which is not radiation-hardened is explained, and then the structure and manufacturing method of a radiation-hardened semiconductor device are described.
First, as a conventional semiconductor for general use, gate array is described by referring to FIGS. 1A and 1B. FIG. 1A is a plan view of this gate array, and FIG. 1B is a sectional view along line K-K' in FIG. 1A.
As shown in FIGS. 1A and 1B, this gate array has a basic cell 34. In an actual gate array, this basic cell 34 is repeatedly developed symmetrically on four sides (broken line in FIG. 1A), and the gate array is composed.
In a PMOS region 31, three P type diffusion layers 15, gate electrodes 18 disposed between the P type diffusion layers, and N type well contacts 16 are formed in the N type well 12 (surface side) on the P type substrate 11, and a pair of P channel MOS transistors are formed. In each one of the NMOS region N 32 and NMOS region N 33 for transfer gate, three N type diffusion layers 14, gate electrodes 18, and P type well contacts 17 are formed in the P type well 13, so that a pair of N channel MOS transistors are formed.
Further, the PMOS region 31 and NMOS region 32, the NMOS region 32 and NMOS region 33 for transfer gate, and the NMOS regions 33 for transfer gate mutually are respectively separated from each other by means of the field oxide film 19. A guard ring boron layer 25 is formed immediately beneath the field oxide film 19 formed at the P type well 13 side.
A manufacturing method of this gate array is described below.
First, the P type substrate 11 is prepared, and N type wells 12 and P type wells 13 are formed selectively. In the N type well region 12, the PMOS region 31 is finally formed, and in the P type well region 13, the NMOS region 32 and NMOS region 33 for transfer gate are finally formed.
Next, to form the guard ring boron layer 25, except for the area for forming N type diffusion layer 14 and P type well contact 17 of the P type well region 13, boron ions are implanted (100 keV, 1.times.10.sup.13 cm.sup.-2). Then, by LOCOS (local oxidation of silicon) method, the field oxide film 19 is formed selectively in other regions than the area for forming N type diffusion layer 14, P type diffusion layer 15, N type well contact 16, and P type well contact 17 in later processes. As a result, the guard ring boron layer 25 is formed beneath the field oxide film 19 at the P type well 13 side.
Afterwards, boron ions are implanted in order to control the threshold voltage of N channel MOS transistor and control the threshold voltage of P channel MOS transistor. Then, a gate electrode 18 is formed.
To form the N type diffusion layer 14 and N type well contact 16, arsenic (or phosphorus) ions are implanted. Similarly, to form the P type diffusion layer 15 and P type well contact 17, boron (or boron fluoride) ions are implanted.
Consequently, by repeated steps of interlayer film growth such as BPSG, formation of contact hole and via hole for electric connection, and formation of aluminum wiring and others, a semiconductor device is completed.
Thus, the gate array for general use is constructed and manufactured.
Next, a radiation-hardened semiconductor device and its manufacturing method are described below.
As shown in FIGS. 2A and 2B, the gate array which is radiation-hardened comprises, in addition to the constitution in FIG. 1, a high concentration guard boron P layer 23 contacting with the field oxide film 19 and N type diffusion layer 14, in order to prevent leakage between source and drain (leakage between the middle diffusion layer and diffusion layers positioned at its both sides, of the three N type diffusion layers 14 in each region) of the N channel MOS transistor formed individually in the NMOS region 32 and NMOS region 33 for transfer gate.
Next, a guard band P layer 24 and a high energy boron implantation P layer 21 are formed in order to prevent leakage between the N type well 12 and the source (or drain) of N channel MOS transistor of the NMOS region 32, to prevent leakage between the source (or drain) of N channel MOS transistor of the NMOS region 32 and the drain (or source) of N channel MOS transistor of the NMOS region 33 for transfer gate, and to prevent leakage between the drain (or source) of N channel MOS transistor of the NMOS region 33 for transfer gate and the source (or drain) of N channel MOS transistor of the adjacent basic cell (at the right side in the drawing, not shown).
Thereafter, a high energy boron implantation P layer 21 is formed between the source (or drain) of N channel MOS transistor for in one of the two NMOS regions 33 for transfer gate, and the drain (or source) of the N channel MOS transistor formed in the other, in order to prevent leakage between them.
A manufacturing method of this semiconductor device is described below.
First, the P type substrate 11 is prepared, and N type wells 12 and P type wells 13 are formed selectively. In the N type well region 12, the PMOS region 31 is finally formed, and in the P type well region 13, the NMOS region 32 and NMOS region 33 for transfer gate are finally formed.
Next, to form the guard ring boron layer 25, except for the area for forming N type diffusion layer 14 and P type well contact 17 of the P type well region 13, boron ions are implanted (100 keV, 1.times.10.sup.13 cm.sup.-2). Then, by LOCOS (local oxidation of silicon) method, the field oxide film 19 is formed selectively in other regions than the area for forming N type diffusion layer 14, P type diffusion layer 15, N type well contact 16, and P type well contact 17 in later processes. As a result, the guard ring boron layer 25 is formed beneath the field oxide film 19 at the P type well 13 side. So far, the process is same as in the manufacturing method of the semiconductor device for general use.
Then a high energy boron implantation P layer 21, a high concentration guard boron P layer 23, and a guard band P layer 24 are formed, by using different masks, by implanting boron ions selectively. Further, boron ions are implanted in order to control the threshold voltage of N channel MOS transistor and control the threshold voltage of P channel MOS transistor. At this time, the sequence of boron ion implantation is not particularly specified.
Then, a gate electrode 18 is formed. To form the N type diffusion layer 14 and N type well contact 16, arsenic (or phosphorus) ions are implanted. Similarly, to form the P type diffusion layer 15 and P type well contact 17, boron (or boron fluoride) ions are implanted.
Finally, by repeated steps of interlayer film growth such as BPSG, formation of contact hole and via hole for electric connection, and formation of aluminum wiring and others, a semiconductor device is completed.
Thus, the gate array which is radiation-hardened is constructed and manufactured.
However, these conventional semiconductor devices have several problems. As a first problem, in the radiation-hardened semiconductor device, as compared with the product for general use, it requires more manufacturing steps, and a longer time in manufacture, and is hence raised in cost.
The reason is that, in order to enhance the resistance to radiation, it requires steps for forming high energy boron implantation P layer, high concentration guard boron P layer, and guard band P layer, in addition to the process of forming the product for general use.
As a second problem, of the three P layers added for enhancing the resistance to radiation, as for the two P layers of high concentration guard boron P layer and guard band P layer, mask data cannot be obtained easily from the layout of the product for general use. It means that the design is difficult for fortifying the resistance to radiation in the LSI for exclusive use such as CPU.
The reason is that the forming positions (shapes) of the high concentration guard boron P layer and guard band P layer do not coincide with other film such as field oxide layer.
As a third problem, in the intersecting portion of the guard band P layer and gate electrode, the parasitic capacity between the gate and substrate increases.
The reason is that the capacity between the gate - electrode and substrate is large in the intersecting portion of the guard band P layer and gate electrode because the field oxide film is thin.